The present invention relates to a semiconductor device of a MIS (metal-insulator-semiconductor) structure, particularly to a semiconductor device comprising metal silicide films formed to cover a gate electrode and source-drain diffusion layers and a method of manufacturing the same.
In recent years, a semiconductor device of a CMOS (Complementary Metal Oxide Semiconductor) structure, which is a typical MIS structure, has achieved marked improvements in the degree of integration by miniaturization and in the operation speed.
With progress in the miniaturization, particularly, in the quarter micron or smaller, a ratio of the delay caused by a parasitic element such as resistance and capacitance to the intrinsic delay component of a transistor is increased, making it absolutely necessary to decrease the resistance of the source-drain regions and the gate electrode in order to achieve a high speed operation of the device.
As a means for decreasing the resistance, known is a salicide structure in which a silicide film is formed selectively to cover source-drain diffusion layers and a gate electrode. For forming the salicide structure, a metal having a high melting point such as Ti, Co, or Ni is deposited by, for example, a sputtering method on a semiconductor substrate having source-drain diffusion layers and a gate electrode formed thereon, followed by applying an annealing treatment to the substrate so as to convert the high melting point metal deposited on the source-drain diffusion layers and the gate electrode into a silicide and subsequently removing selectively the unreacted high melting point metal. As a result, a silicide film of a low resistivity is formed by self-alignment selectively on the source-drain diffusion layers and the gate electrode. The structure formed by the particular method of forming a silicide film is called a salicide structure.
FIG. 1 is a cross sectional view exemplifying a basic construction of a field effect transistor of MOS structure (MOS-FET) using the salicide structure. As shown in the drawing, a well 108 is formed within a silicon semiconductor substrate 101. A gate electrode 103 consisting of polycrystalline silicon is formed on a surface of the well 108 with a gate oxide film 102 interposed therebetween. A gate side wall film 104 consisting of a silicon nitride film is formed on the side surface of the gate electrode 103.
Further, a shallow source-drain diffusion layer 105 and a deep source-drain diffusion layer 106 are formed below the gate side wall film 104. Still further, a silicide film 107 is formed on the deep source-drain diffusion layer 106 and on the gate electrode 103.
The silicide film 107 is formed as follows. Specifically, after formation of the deep source-drain diffusion layer 106, a metal film having a high melting point is deposited in a thickness of about 30 nm on the semiconductor substrate including the deep source-drain diffusion layer 106 and the gate electrode 103. Then, an annealing treatment is applied to the metal film on the deep source-drain diffusion layer 106 and the gate electrode 103 so as to convert the metal layer into a silicide layer, followed by selectively removing the unreacted high melting point metal. As a result, the silicide film 107 is formed by self-alignment on selectively the deep source-drain diffusion layer 107 and the gate electrode 103.
In the semiconductor device employing the conventional salicide structure as shown in FIG. 1, it is necessary to form the source-drain diffusion layer deep. Where the source-drain diffusion layer is formed shallow, silicon in the source-drain diffusion layer is consumed in the step of forming the silicide in the salicide structure, with the result that leakage at the junction is generated. Incidentally, a ratio in the thickness of the consumed silicon film to a unit thickness of the metal film in the step of forming the silicide is 2.27 in the case of forming titanium silicide (TiSi2), 3.64 in the case of forming cobalt silicide (COSi2) and 1.83 in the case of forming nickel silicide (NiSi).
It should be noted that, where a shallow junction is formed as a source-drain diffusion layer in the MOS-FET using the conventional silicide film, a junction leakage is generated at the shallow junction portion. In order to prevent the junction leakage, it is necessary to form a deep junction as a source-drain diffusion layer.
Let us describe the problem which is to be solved by the present invention.
As described above, if a deep junction is formed as a source-drain diffusion layer, generation of a short channel effect is rendered prominent in the MOS-FET. As a result, it is necessary to ensure a sufficient width of the gate side wall film, which inhibits miniaturization of the semiconductor device.
In the case of employing the salicide structure, the contact resistance at the interface between the silicide film and the silicon layer and the resistance of the shallow junction portion occupy a very high ratio relative to the entire parasitic resistance at the source-drain diffusion layer. Thus, the parasitic resistance is not significantly changed even if the sheet resistance of the silicide film formed on the diffusion layer is changed. It follows that, if the parasitic resistance is set at about 5% of the intrinsic resistance, it is possible to decrease the thickness of the silicide film formed on the diffusion layer, though it is necessary to diminish the parasitic resistance with progress in miniaturization of the semiconductor device.
On the other hand, in order to achieve a high speed-operation, it is necessary to decrease the gate delay time of, for example, the CMOS inverter. To achieve the object, it is necessary to form a gate electrode of a low resistance.
FIG. 2 shows the sheet resistance of a silicide film positioned on the source-drain diffusion layer and on the gate electrode required for the gate length of each semiconductor era.
On the other hand, the sheet resistance of a silicide film is inversely proportional to the thickness of the silicide film, if it is assumed for the sake of simplification that the resistivity of the silicide film does not depend on the size, that is, if it is assumed that a so-called “fine wire effect” does not exist and, thus, the resistivity of the silicide film is not changed by the thinning of the film. It follows that it is necessary to increase in the future the thickness of the silicide film positioned on the gate electrode with decrease in the gate length.